Sequential logic circuits are used extensively in the design of electronic circuits. FIG. 1 depicts a typical sequential logic circuit 100. Stages 101-104 are coupled together in a series configuration, i.e. the output of each non-terminal stage 101-103 feeds the input of the following stage. Each stage includes a clocked bistable element 105-108, such as a flip-flop or a latch, for the synchronous transfer of data. Each non-terminal stage also includes a combinational logic block 109-111 for the manipulation of data. Two clocking schemes are prevalent in such a typical sequential logic circuit. The first, generally preferred when using flip-flops, is to clock all of the bistable elements with a single free running clock. The second, generally preferred when using latches, is to clock all of the bistable elements in an odd numbered stage with a single free running clock and to clock all of the bistable elements in an even numbered stage with the complement of the single free running clock.
When either of these two clocking schemes is used, the power consumed by the sequential logic circuits is often a major component of the total power consumed by an entire electronic circuit, such as a microprocessor. Since the reduction of power consumption is currently one of the key goals of electronic circuit designers, a novel scheme of clocking sequential logic circuits is desired.